Title: Simulation on highly parallel architectures
Abstract: In the future the classic microprocessor will be replaced with a highly parallel chip multiprocessor. Conventual CPUs will have many cores; graphic processors (GPUS) will have hundreds of floating point units; new architectures like Cell will also become ubiquitous. This talk will review recent developments in these areas
and their impact on SimBIOS. I will also report on joint
work with V. Pande, E. Darve and A. Lew. For example, we
have recently implemented an nbody code that runs 40x
faster on the ATI 580 than on a P4. Similar speedups
have been realized with HMMER (hidden markov models)
and mechanics code. The software and hardware has developed
to the point where we can now impact the basic science.
